View ZL30462_276516.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ZL30462 Timing Module
Data Sheet Features
* * * Complete timing solution in a small outline package Selectable 8kHz, 1.544MHz, 2.048MHz or 19.44MHz input reference frequencies 8kHz (frame pulses), 2.048MHz, 8.192MHz, 16.384MHz, 19.44MHz and 155.52MHz (LVPECL) output clock frequencies Low intrinsic jitter and wander generation Fast lock and automatic holdover modes Holdover and lock indication Provides Time Interval Error (TIE) correction Accepts reference inputs from two independent sources 3.3V Supply Voltage Ordering Information ZL30462/MCG 40 SMT DIL (Tray + dry packed)
April 2003
0C to +70C
* * * * * *
Description
The ZL30462 is a Timing Module, which functions as a complete system clock solution for general timing applications. The ZL30462 has been designed around Zarlink's Digital and Analog Phase Locked Loop (DPLL and APLL) technology and can lock to 1 of 2 inputs which can be derived from 2 independent sources. The module has two jitter attenuated output clocks at 19.44MHz (CMOS) and 155.52MHz (LVPECL). In addition to these outputs the module also supplies 2 8kHz frame pulses and 2.048MHz, 8.192MHz and 16.384MHz clocks.
Applications
* * * * SDH Add/Drop multiplexers Next Gen Digital Loop Carriers ATM edge switches Line cards
/TC LR
FS 1
FS 2
TV dd
TG N D
OSC
V dd
AGND
Frequency S elect MUX
M aster O scillator O utput Interface C ircuit D P LL
/C 16o C 8o C 2o /F16o LK 1 (F8o)
PRI SEC
R eference S elect MUX
T IE C orrector C ircuit Inp ut Im prairm ent M onitor A P LL
LK 2 JA 19M o C onverter JA 155P /N
RSEL
C ontrol S tate M achine
Loop Filter
MS1
M S 2 /R E S E T P C C i
H O LD O V E R
FLO C K LO C K
Figure 1 - Functional Block Diagram
1
ZL30462
Data Sheet
1
40
20
21
Figure 2 - 40 Pin SMT DIL Top View Pin Description Table Pin Number 1 2 3 4 Name C16o C8o C2o F16o Description Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a 16.384MHz clock. Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s. Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s. Frame Pulse ST-BUS 16.384Mb/s (CMOS Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS operation at 16.384Mb/s. Link1. Connect this pin to pin 6. This pin is also the F8o (8kHz 122ns) active high frame pulse, which marks the beginning of a frame and is also used by the DPLL's state machine. See Section 1.7 State Machine Control. Link2. Connect this pin to pin 5. Ground. Internal Connection. Do not connect to this pin. Internal Connection. Do not connect to this pin. Ground. Internal Connection. Do not connect to this pin. Internal Connection. Do not connect to this pin. Positive Power Supply. 3.3V Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to the input reference. Clock 19.44MHz (CMOS Output). This output provides a low jitter 19.44MHz clock.
5
LK1 (F8o) LK2 AGND1 IC IC AGND1 IC IC VDD2 LOCK JA19Mo
6 7 8 9 10 11 12 13 14 15
2
Zarlink Semiconductor Inc.
Data Sheet
Pin Description Table (continued) Pin Number 16 17 18 19 20 21 22 23 24 25 Name JA155N JA155P AGND2 VDD3 AGND1 TVDD TGND OSC VDD1 PRI Description
ZL30462
JA 155.52MHz Clock (LVPECL Output). This differential output provides a low jitter 155.52MHz clock. Ground. Positive Power Supply.3.3V Ground. Oscillator Positive Power Supply. 3.3V Oscillator Ground. Oscillator Master Clock (CMOS Output). This pin can be used to monitor the output of the on-board master oscillator. Positive Power Supply. 3.3V Primary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the MS1, MS2, FS1, FS2, and RSEL control inputs.This pin is internally pulled up to VDD. Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources (falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the MS1, MS2, FS1, FS2, and RSEL control inputs.This pin is internally pulled up to VDD. Internal Connection. Do not connect to this pin. TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase. To ensure correct operation of this function, the TCLR pin should be held low for a minimum of 300ns. This pin is internally pulled down to GND. Reset (Input). A logic low at this input resets the DPLL. To ensure proper operation, the device must be reset after reference signal frequency changes and power-up. The RESET pin should be held low for a minimum of 300ns. While the RESET pin is low, all frame and clock outputs are at logic high. Following a reset, the input reference source and output clocks and frame pulses are phase aligned. Ground. Internal Connection. Do not connect to this pin. Frequency Select 1 (Input). This input, in conjunction with FS2, selects which of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and SEC inputs. See Table 1. Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI and SEC inputs. See Table 1. Reference Source Select (Input). A logic low selects the PRI (primary) reference source as the input reference signal and a logic high selects the SEC (secondary) input. This pin is internally pulled down to GND. See Table 2. Mode/Control Select 1 (Input). This input, in conjunction with MS2, determines the state (Normal, Holdover or Freerun) of operation. See Table 3. Mode/Control Select 2 (Input). This input, in conjunction with MS1, determines the state (Normal, Holdover or Freerun) of operation. See Table 3.
26
SEC
27 28
IC TCLR
29
RESET
30 31 32
AGND1 IC FS1
33
FS2
34
RSEL
35 36
MS1 MS2
Zarlink Semiconductor Inc.
3
ZL30462
Pin Description Table (continued) Pin Number 37 Name PCCi Description
Data Sheet
Phase Continuity Control Input (Input). The signal at this pin affects the state changes between Holdover and Normal Modes. The logic level at this input is gated in by the rising edge of F8o (LK1). See Table 4. HOLDOVER (CMOS Output). This output goes to a logic high whenever the PLL goes into holdover mode. Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less than 500 ms locking time). Positive Power Supply. 3.3V
38 39 40
HOLDOVER FLOCK VDD1
1.0
Functional Description
The ZL30462 offers a complete timing solution in a 1" x 1" module package. The module comprises 3 main components, a DPLL which performs the main operational functions, a APLL which provides 2 low jitter output clocks and an on-board master oscillator. Figure 1 shows a functional block diagram of the module, which is described in the following sections.
1.1
Reference Select MUX Circuit
The ZL30462 accepts two simultaneous reference input signals and operates on their falling edges. Either the primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1 and Table 4.
1.2
Frequency Select MUX Circuit
The ZL30462 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RESET) must be performed after every frequency select input change. See Table 1.
FS2 0 0 1 1
FS1 0 1 0 1 19.44MHz 8kHz 1.544MHz 2.048MHz
Input Frequency
Table 1 - Input Frequency Selection
1.3
Time Interval Error (TIE) Corrector Circuit
The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or SEC) from causing a step change in phase at the input of the DPLL block of Figure 1. During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL would lead to unacceptable phase changes in the output signal.
4
Zarlink Semiconductor Inc.
Data Sheet
ZL30462
As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference, which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.
/TCLR Resets Delay
Control Circuit
Control Signal
Delay Value Virtual Reference to DPLL Compare Circuit
PRI or SEC from Reference Select MUX
Programmable Delay Circuit
TIE Corrector Enable from State Machine
Feedback Signal from Frequency Select MUX
Figure 3 - TIE Corrector Circuit During a switch from one reference to the other, the State Machine first changes the mode of the device from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value is passed to the Programmable Delay Circuit (See Figure 3). The new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch not taken place. The State Machine then returns the device to Normal Mode. The DPLL now uses the new virtual reference signal, and since no phase step took place at the input of the DPLL, no phase step occurs at the output of the DPLL. In other words, reference switching will not create a phase change at the input of the DPLL, or at the output of the DPLL. Since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the DPLL. This phase error is a function of the difference in phase between the two input reference signals during reference rearrangements. Each time a reference switch is made, the delay between input signal and output signal will change. The value of this delay is the accumulation of the error measured during each reference switch. The programmable delay circuit can be zeroed by applying a logic low pulse to the TIE Circuit Reset (TCLR) pin. The minimum reset pulse width is 300ns. The speed of the phase alignment correction is limited to 5ns per 125s, and convergence is in the direction of least phase travel. The state diagram of Figure 8 indicates which state changes the TIE Corrector Circuit is activated.
Zarlink Semiconductor Inc.
5
ZL30462
1.4 Digital Phase Lock Loop (DPLL)
Data Sheet
As shown in Figure 8, Control State Diagram consists of a Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator, and a Control Circuit.
Virtual Reference from TIE Corrector
Phase Detector
Limiter
Loop Filter
Digitally Controlled Oscillator
DPLL Reference to Output Interface Circuit
Feedback Signal from Frequency Select MUX
State Select from Input Impairment Monitor State Select from State Machine
Control Circuit
Figure 4 - DPLL Block Diagram
1.4.1
Phase Detector
The Phase Detector compares the virtual reference signal from the TIE Corrector circuit with the feedback signal from the Frequency Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the Limiter circuit. The Frequency Select MUX allows the proper feedback signal to be externally selected (e.g., 8kHz, 1.544MHz, 2.048MHz or 19.44MHz).
1.4.2
Limiter
The Limiter receives the error signal from the Phase Detector and ensures that the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125s. This is well within the maximum phase slope of 7.6ns per 125s or 81ns per 1.326ms specified by AT&T TR62411 and Telcordia GR-1244-CORE, respectively.
1.4.3
Loop Filter
The Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four reference frequency selections (8kHz, 1.544MHz, 2.048MHz or 19.44MHz). This filter ensures that the jitter transfer requirements in ETS 300 011 and AT&T TR62411 are met.
1.4.4
Control Circuit
The Control Circuit uses status and control information from the State Machine and the Input Impairment Circuit to set the mode of the DPLL. The three possible modes are Normal, Holdover and Freerun.
6
Zarlink Semiconductor Inc.
Data Sheet
1.4.5 Digitally Controlled Oscillator (DCO)
ZL30462
The DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30462. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In Holdover Mode, the DCO is free running at a frequency equal to the last (30ms to 60ms) frequency the DCO was generating while in Normal Mode. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSC 20MHz source.
1.4.6
Lock Indicator
If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to the line frequency), and the input phase offset is small enough such that no phase slope limiting is exhibited, then the lock signal will be set high.
1.5
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure 5. The Output Interface Circuit uses a Tapped Delay Line followed by a E1 Divider Circuit to generate the required output signals. A tapped delay line is used to generate a 16.384MHz signal. The E1 Divider Circuit uses the 16.384MHz signal to generate three output clocks and two frame pulses. The C8o and C2o clocks are generated by simply dividing the C16o clock, by two and eight respectively. These outputs have a 50% duty cycle. The F8o and F16o frame pulse outputs are also generated from this 16.384MHz signal. Both frame pulse outputs have limited drive capability and should be buffered when driving high capacitance (e.g., 30pF) loads.
F8o From DPLL Tapped Delay Line 16.384MHz /F16o E1 Divider C2o C8o /C16o
Figure 5 - Output Interface Circuit Block Diagram
1.6
Input Impairment Monitor
This circuit monitors the input signal to the DPLL and automatically enables the Holdover Mode (Auto-Holdover) when the frequency of the incoming signal is outside the Auto-Holdover capture range. (See AC Electrical Characteristics - Performance). This includes a complete loss of incoming signal, or a large frequency shift in the incoming signal. When the incoming signal returns to normal, the DPLL is returned to Normal Mode with the output signal locked to the input signal. The holdover output signal in the ZL30462 is based on the incoming signal 30ms minimum to 60ms prior to entering the Holdover Mode. The amount of phase drift while in holdover is negligible because the Holdover Mode is very accurate (e.g., 0.05ppm, relative to the master oscillator frequency). Consequently, the phase delay between the input and output after switching back to Normal Mode is preserved.
Zarlink Semiconductor Inc.
7
ZL30462
1.7 State Machine Control
Data Sheet
As shown in Figure 1, this state machine controls the Reference Select MUX, the TIE Corrector Circuit and the DPLL. Control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). When switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and disabled when PCCi = 0. All state machine changes occur synchronously on the rising edge of F8o (internal 8kHz frame pulse), this signal is available form pin 3 (LK1). See the Control and Mode of Operation section for full details.
To Reference Select MUX
To TIE Corrector Enable
To DPLL State Select
RSEL
Control State Machine
PCCi
MS1
MS2 /RESET HOLDOVER
Figure 6 - Control State Machine Block Diagram
1.8
Master Oscillator
The ZL30462 uses a 20MHz 20ppm master oscillator, the output frequency of the oscillator can be monitored via the OSC pin. The on-board master oscillator is powered via the TVDD and TGND pins, independently of the modules VDDx and AGNDx pins,
8
Zarlink Semiconductor Inc.
Data Sheet 2.0 Control and Mode of Operation
ZL30462
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and Figure 8 for details of the state change sequences.
RSEL 0 1 PRI SEC
Input Reference
Table 2 - Input Reference Selection The ZL30462 has three possible modes of operation, Normal, Holdover and Freerun. As shown in Table 3, Mode/Control Select pins MS2 and MS1 select the mode and method of control.
MS2 0 0 1 1
MS1 0 1 0 1 NORMAL HOLDOVER FREERUN Reserved
Mode
Table 3 - Operating Modes and States
2.1
Normal Mode
Normal Mode is typically used when a slave clock source, synchronized to the network is required. In Normal Mode, the ZL30462 provides timing (C2o, C8o, C16o, JA19Mo and JA155P/N) and frame synchronization (F8o & F16o) signals, which are synchronized to one of two reference inputs (PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz, 2.048MHz or 19.44MHz. From a reset condition, the ZL30462 will take up to 30 seconds (see AC Electrical Characteristics) for the output signals to be synchronized (phase locked) to a valid reference input. The selection of input references is control dependent as shown in state Table 4. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1. During normal mode, whilst locked to a synchronization source input, the ZL30462 can tolerate a 10ppm frequency change (on that input) without generating alarms or charging state.
2.2
Fast Lock Mode
Fast Lock Mode is a sub-mode of Normal Mode, it is used to allow the ZL30462 to lock to a reference more quickly than Normal Mode will allow. Typically, the DPLL will lock to the incoming reference within 500ms if the FLOCK pin is set high.
Zarlink Semiconductor Inc.
9
ZL30462
2.3 Holdover Mode
Data Sheet
Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is temporarily disrupted. In Holdover Mode, the ZL30462 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30462 output reference frequency is stored alternately in two memory locations every 30ms. When the device is switched into Holdover Mode, the value in memory from between 30ms and 60ms is used to set the output frequency of the device. The frequency accuracy of Holdover Mode is 0.05ppm, which translates to a worst case 35 frame (125s) slips in 24 hours. This satisfies the AT&T TR62411 and Telcordia GR-1244-CORE Stratum 3 requirement of 0.37ppm (255 frame slips per 24 hours). Two factors affect the accuracy of Holdover Mode. One is drift on the master oscillator whilst in Holdover Mode, drift on the master oscillator directly affects the Holdover Mode accuracy. The other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch. For instance, jitter of 7.5UI at 700Hz may reduce the Holdover Mode accuracy from 0.05ppm to 0.10ppm.
2.4
Freerun Mode
Freerun Mode is typically used when a master clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun Mode, the ZL30462 provides timing and synchronization signals which are based on the master oscillator frequency (OSC) only, and are not synchronized to the reference signals (PRI and SEC). The accuracy of the output clock is equal to the accuracy of the master oscillator (OSC) which is 20ppm.
2.5
Reset Circuit
A simple power up reset circuit with about a 50s reset low time is shown in Figure 7. Resistor Rp is for protection only and limits current into the RESET pin during power down conditions. The reset low time is not critical but should be greater than 300ns.
ZL30462
R 10k ______ RESET
Vdd
Rp 1k
C 10nF
Figure 7 - Power-Up Reset Circuit
2.6
Warm-up Time
The ZL30462 should have a warm-up time of 10 hours to ensure that the module has reached a stable operating temperature (however reasonable operation can be expected with 30 minutes).
10
Zarlink Semiconductor Inc.
Data Sheet 3.0 ZL30462 Measures of Performance
ZL30462
The following are some synchronizer performance indicators and their corresponding definitions.
3.1
Intrinsic Jitter
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode, such as free running or holdover, by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards. To enhance the performance of the ZL30462 an additional APLL has been incorporated to provide two low jitter output. The JA155P/N (LVPECL) and JA19Mo (single ended) outputs both offer better than OC3 jitter performance.
3.2
Jitter Tolerance
Jitter tolerance is a measure of the ability of the ZL30462 to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards.
3.3
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, output jitter is measured with various filters, dependant on the required standard.
3.4
Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the ZL30462, the Freerun accuracy is equal to the Master Oscillator (OSC) accuracy.
3.5
Holdover Accuracy
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30462, the storage value is determined while the device is in Normal Mode and locked to an external (and stable) reference signal for at least 10 minute after the warm-up period. The absolute Master Oscillator (OSC) accuracy of the ZL30462 does not affect Holdover accuracy, but the change in OSC accuracy while in Holdover Mode does.
3.6
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull into synchronization. The ZL30462 capture range is equal to 230 ppm, which is offset by the accuracy of the Master Oscillator (OSC).
3.7
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the ZL30462.
3.8
Phase Slope
Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal.
Zarlink Semiconductor Inc.
11
ZL30462
3.9 Time Interval Error (TIE)
Data Sheet
TIE is the time delay between a given timing signal and an ideal timing signal.
3.10
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period.
N-n+1 MTIE(S) = max j=1 n+j-1 max(x ) i i=j n+j-1
-
min(x ) i i=j
3.11
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. In the case of the ZL30462, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of all reference switches and all mode changes. The total phase shift, depending on the switch or type of mode change, may accumulate up to 200ns over many frames. The rate of change of the 200ns phase shift is limited to a maximum phase slope of approximately 5ns/125s. This meets the AT&T TR62411 maximum phase slope requirement of 7.6ns/125s and Telcordia GR-1244-CORE (81ns/1.326ms).
3.12
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). Lock time is very difficult to determine because it is affected by many factors which include: * * * * initial input to output phase difference initial input to output frequency difference synchronizer loop filter synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. The ZL30462 loop filter and limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently, phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical Characteristics - Performance for Maximum Phase Lock Time.
12
Zarlink Semiconductor Inc.
Data Sheet
ZL30462
Description Input Controls Freerun PCCi 0 1 X X X X S0 S1 S1 S2 / / Normal PRI S1 S2 MTIE S1H / S0 State Normal SEC S2 S1 MTIE S1 MTIE / S2H S0 Holdover PRI S1H S1 S1 MTIE S2 MTIE / S0 Holdover SEC S2H S1 MTIE S1 MTIE S2 MTIE / S0
MS2 0 0 0 0 0 1
MS1 0 0 0 1 1 0
RSEL 0 0 1 0 1 X
Legend: No Change / Not Valid MTIE State change occurs with TIE Corrector Circuit Refer to Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Control State Table
S0 Freerun (10X)
S1 Normal Primary (000)
{A}
S1A Auto-Holdover Primary (000)
S2A Auto-Holdover Secondary (001)
{A}
S2 Normal Secondary (001)
(PCCi=0) (PCCi=1)
S1H Holdover Primary (010)
S2H Holdover Secondary (011)
NOTES: (XXX) MS2 MS1 RSEL {A} Invalid Reference Signal Movement to Normal State from any state requires a valid input signal
Phase Re-Alignment Phase Continuity Maintained (without TIE Correction Circuit) Phase Continuity Maintained (with TIE Correction Circuit)
Figure 8 - Control State Diagram
Zarlink Semiconductor Inc.
13
ZL30462
4.0
4.1
Data Sheet
Characteristics
AC and DC Electrical Characteristics
Absolute Maximum Ratings* Parameter 1 Supply Voltages Symbol VDD TVDD Min -0.3 -0.3 Max 5.0 5.0 Units V V V
2 Input Voltage VIN -0.05 VDD+0.5 * Voltages are with respect to ground (GND) unless otherwise stated * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions* Parameter 1 2 Supply Voltages Operating Temperature Symbol VDD TVDD TA Min 3.0 0 Typ 3.3 25 Max 3.6 70
Units V
C
* Voltages are with respect to ground (GND) unless otherwise stated
DC Electrical Characteristics* Characteristics 1 2 3 4 5 6 7 8 9 10 11 Supply Current Supply Current CMOS: High-level input voltage CMOS: Low-level input voltage CMOS: Input leakage current CMOS: High-level output voltage CMOS: Low-level output voltage LVPECL: Differential output voltage LVPECL: High-level output voltage LVPECL: Low-level output voltage LVPECL: Output rise and fall times Symbol IDD TIDD VIH VIL IIL VOH VOL |VOD| VOH VOL TRF 250 480 600 VDD-0.9 VDD-1.5 300 700 2.4 0.4 720 0.7VDD 0 0.3VDD 15 Min Typ 93 5 Max 105 10 Units mA mA V V A V V mVp V V ps Note 1 VI=VDD or GND IOH = 8mA IOL = 8mA ZT=100 Ohms ZT=100 Ohms Test Conditions Output unloaded Output unloaded
* Voltages are with respect to ground (GND) unless otherwise stated Note 1: Rise and fall times are measured at 20% and 80% levels. * Voltages are with respect to ground (GND) unless otherwise stated
14
Zarlink Semiconductor Inc.
Data Sheet
AC Electrical Characteristics* Parameter 1 2 3 4 Freerun Mode accuracy Holdover Mode accuracy Capture range Intrinsic Jitter 500Hz - 1.3MHz 65kHz - 1.3MHz Wander Generation Wander Transfer Phase response to input signal interruptions Phase Transients Holdover Entry Phase Transients Lock Time JIN 500 400 WGEN WTR PTT PT HEPT LT 30 s ps ps Symbol FA Min -20 FA-0.05 FA-230 Max 20 FA+0.05 FA+230 Units ppm ppm ppm
ZL30462
Test Conditions Note 2 Note 3 Note 4 Note 5
5 6 7 8 9 10
Note 2: Note 3: Note 4: Note 5:
ITU-T G.813 Option1 ITU-T G.813 Option1 ITU-T G.813 Option1 ITU-T G.813 Option1 ITU-T G.813 Option1
The Freerun accuracy is directly related to the accuracy of the master oscillator The DPLL Holdover accuracy is also affected by the holdover stability of the master oscillator This figure is offset by the accuracy of the master oscillator Applies to JA outputs only
AC Electrical Characteristics* - Timing Parameter Measurements - CMOS Voltage Levels* Characteristics 1 2 3 Threshold voltage Rise and fall threshold voltage High Rise and fall threshold voltage Low Symbol VT VHM VLM Typical 0.5VDD 0.7VDD 0.3VDD Units V V V
* Voltages are with respect to ground (GND) unless otherwise stated
Timing Reference Points
All Signals
V HM VT V LM
T IF, TOF
T IR, TOR
Figure 9 - Timing Parameters Measurement Voltage Levels
Zarlink Semiconductor Inc.
15
ZL30462
AC Electrical Characteristics - Input Phase Alignment Characteristics 1 2 3 4 5 6 7 8 9 8kHz ref. pulse width low 8kHz ref. input to F8o delay 1.544MHz ref. pulse width low 1.544MHz ref. input to F8o delay 2.048MHz ref. pulse width low 2.048MHz ref. input to F8o delay 19.44MHz ref. pulse width low 19.44MHz ref. input to F8o delay Reference input rise and fall time Symbol tR8H tR8D tR1.5L tR1.5D tR2L tR2D tR19L tR19D tIR, tIF Min 100 -21 100 337 100 222 23 46 57 10 238 363 6 Max Units ns ns ns ns ns ns ns ns ns
Data Sheet
Test Conditions
t R8H t R8D PRI/SEC 8kHz tc = 125s t R1.5L tR1.5D VT tc = 647.67ns t R2L t R2D VT tc = 488.28ns t R19L t R19D VT tc = 51.44ns VT
PRI/SEC 1.544MHz
PRI/SEC 2.048MHz
PRI/SEC 19.44MHz
F8o tc = 125s
VT
Figure 10 - Input to Output Timing (Normal Mode)
16
Zarlink Semiconductor Inc.
Data Sheet
AC Electrical Characteristics - Input Control Signals Characteristics 1 2 Input Controls Setup Time Input Controls Hold Time Symbol tS tH Min 100 100 Max Units ns ns
ZL30462
Test Conditions
F8o tS tH
VT
M MS2, S1, RSEL, PCCi
VT
Figure 11 - Input Control Signal Setup and Hold Time
AC Electrical Characteristics - Outputs Timing Characteristics 1 2 3 4 5 6 F8o to F16o delay F8o to JA155P/N delay F8o to JA19Mo delay F8o to C16o delay F8o to C8o delay F8o to C2o delay Symbol tF16D tJ155PD tJ155ND tJ19D tC16D tC8D tC2D Min 22 -5 -5 -5 -11 -11 -11 Max 37 10 10 10 5 5 5 Units ns ns ns ns ns ns ns Test Conditions
Zarlink Semiconductor Inc.
17
ZL30462
Data Sheet
F8o tc = 125s
VT t F16D
/F16o
VT t J155PD VT t J155ND VT t J19D
tc = 125s
JA155P tc = 6.43ns JA155N tc = 6.43ns
JA19Mo tc = 51.44ns /C16o tc = 61.035ns
VT t C16D VT t C8D
C8o tc = 122.07ns
VT t C2D
C2o tc = 488.28ns
VT
Figure 12 - Output Timing
18
Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
1 214170 26Mar03
For more information about all Zarlink products visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request.
Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE

▲Up To Search▲

Price & Availability of ZL30462

	To Download ZL30462 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .